A gate insulating film of an MISFET (Metal Insulator Semiconductor Field Effect Transistor) fabricated using a single crystal silicon wafer requires a high performance electric characteristics such as a low leakage current characteristic, a low interface state density and a high resistance to ion implantation and a high reliability. The main stream in techniques for forming a gate insulating film satisfying the requirements is a technique for formation of a silicon dioxide film (hereinafter also simply referred to as an oxide film) using a thermal oxidation. This technique is a so-called MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). With the thermal oxidation, in a case where a silicon wafer with a {100} plane as a main surface thereof, a good oxide film of a silicon interface characteristic, a dielectric breakdown voltage characteristic and a leakage current characteristic can be ensured. A major reason why a silicon wafers with a {110} plane or a {111} plane other than the {100} plane as a main surface is not used as a substrate of an integrated circuit device is that an interface state density of an oxide film formed on the {110} plane or the {111} plane is high. A wafer with a high interface state density is poor in electric characteristics such as a dielectric breakdown voltage characteristic and a leakage current characteristic.
Hence, a silicon wafer substrate on which MOSFETs are fabricated has been a wafer having a main surface having a {100} plane or an inclined plane with an off-angle of about 4 degrees against the {100} plane.
In a semiconductor device fabricated on a substrate having a {100} plane as a main surface, however, there has been a problem that a p-type FET has current driving ability, that is carrier mobility, about 0.3 time as large as an n-type FET. In recent years, there has been developed a method for forming a good quality insulating film without dependence on a plane orientation of a silicon wafer, that is a radical oxidation method, or a radical nitriding method (2000 Symposium on VLSI Technology, Honolulu, Hi., Jun. 13 to 15, 2000, “Advanced of Radical Oxidation for Improving Reliability of Ultra-Thin Gate Oxide”). With this method applied, a good insulating film can be formed on a wafer surface with a plane other than {100}.
Hence, there is highly feasible a semiconductor integrated circuit device fabricated using a silicon semiconductor substrate having a {110} plane as a main surface thereof on which a carrier mobility in a channel direction of MOSFET may be raised. The inventors fabricated a semiconductor device having a main surface of the {110} plane and evaluated characteristics thereof, whereby various kinds of findings were obtained.
The current driving ability of the above p-type FET on a substrate with a {110} plane is increased against the one on a substrate with a {100} plane by about 2.5 times, while the current driving ability of the n-type FET on a substrate with a {110} plane is reduced against the one on a substrate with a {100} plane, which is contrary to expectation. If the electron mobility in the n-type FET can be raised to a value equal to or more than that in a {100} plane, a semiconductor integrated circuit device using a substrate with a {110} plane will be practically and widely used.
There have effects on carrier mobility impurity scattering, phonon scattering (lattice vibration scattering), and surface roughness scattering. When the influences of these scattering are large, the carrier mobility is decreased. Electron mobility on a surface with a {100} plane is greatly affected by roughness of a silicon surface and it has been made definite that the worse the roughness, the lower the electron mobility (T. Ohmi et al.: IEEE Trans Electron Devices, vol. 137, p. 537, 1992). Thereafter, the following two methods have been proposed for the purpose to reduce the surface roughness. That is, (1) formation of an oxide film on a surface of a semiconductor substrate in an atmosphere including oxygen radicals (M. Nagamine et al., IEDM Tech. Dig. p. 593, 1998) and (2) a cleaning method for a substrate surface except for RCA cleaning (W. Kern et al.: RCA Review, vol. 31, p. 187, 1970).
In the radical oxidation adopted by the above method (1), by the synergistic effects that the oxygen radicals, which are oxidation species, have a high probability of attaching to projections on a silicon surface and oxygen ions of O+ and O2+ are attracted to the projections charged negatively, the projections are conceivably oxidized with priority, whereby the surface roughness is reduced. By the oxidation in a conventional atmosphere of dry oxygen, the surface roughness is degraded by about 20%, whereas by the radical oxidation, the surface roughness is reduced by about 40%.
The above cleaning method (2) has been disclosed in JP A No. 11-057636. Since a cleaning step with an alkali solution in the RCA cleaning, which has conventionally been widely used, degrades the surface roughness, the cleaning method disclosed in JP A No. 11-057636 is a cleaning process including no alkali solution and has an ability of removing particles, organic contaminant, and metallic impurities, equal to or more than the RCA cleaning. Since this new cleaning process is constituted of 5 (five) steps, the process is hereinafter referred to as five-step cleaning for short in the present specification.
The reason why the surface roughness is degraded in a cleaning step including an alkali solution in the RCA cleaning is that a portion with a weak Si—Si bond is preferentially etched by hydroxide ions (OH ions).
Of the above two methods for decreasing the surface roughness, the radical oxidation method (1) is a method for reducing the surface roughness, whereas the five step cleaning (2) is a method for suppressing roughening in the RCA leaning rather than a method for reducing a surface roughness. In fact, while the surface roughness is degraded by about 50% in the conventional RCA cleaning, the five step cleaning can restrict degradation of the surface roughness to 0% to 10%.
Since the surface roughness is reduced by the radical oxygen method, the surface roughness can be further reduced by repetition of the radical oxidation prior to formation of a gate oxide film, but the repetition may leads to an ill effect. The radical oxidation is conducted at a low temperature of the order in the range of from 300° C. to 500° C. At this temperature, an oxygen donor is formed to change electric resistivity in the interior of a substrate. If oxidation is performed at a temperature of 500° C. or higher, formation and growth of oxygen precipitation nuclei also occur in a surface layer of a substrate, which leads leakage current and dielectric breakdown of a gate oxide film.
To decrease the surface roughness of a silicon semiconductor substrate is to planarize the surface thereof at an atomic level. A mirror polished and cleaned surface of a silicon wafer having a specific crystal plane has numberless irregularities at an atomic level, which lead to surface roughness called microroughness. The microroughness is formed by generation of many microfacets different from the cutting plane by a chemical reaction of a chemical solution used in polishing and cleaning with a silicon surface.
Since a silicon wafer sliced so as to have a {111} plane as a cutting plane is easy to form a planar surface at an atomic level since a {111} plane itself is a facet plane. Y. J. Chabal et al. have publicly reported that dangling bonds (covalent bonds without counterparts) of silicon atoms at a surface are stabilized at terminating portions by joining hydrogen atoms thereto, thereby the surface being planarized (Y. J. Chabal et al., J. Vac. Sci. & Technol. Vol. A7, pp. 2104, 1989).
It has been made clear that a main surface of a substrate having a {111} plane as the main surface thereof is slightly inclined toward a [112] orientation or a [112] orientation by a few degrees, and is cleaned with an ammonium fluoride aqueous solution, whereby steps and terraces are formed on the surface at an atomic level with the result that the surface is allowed to be flat at an atomic level (H. Sakaue et al., Appl. Phys. Lett. Vol. 78, p. 309, 2001). There has been no report, however, that planarization of a mirror polished silicon substrate having a {100} plane as a main surface, which has been most widely used, is realized at an atomic level only by cleaning the substrate.
There has been a report that in an epitaxial silicon semiconductor substrate epitaxially grown on the main surface thereof having an orientation slightly inclined from a {100} plane, the surface roughness is reduced by forming steps and terraces on the main surface thereof (K. Izunome et al.: Jpn. J. Appl. Phys. Vol. 31, pp. L1277.1992). Besides, there has also been a report that steps and terraces are formed on a silicon semiconductor substrate by applying high temperature heat treatment in a hydrogen atmosphere to thereby reduce the surface roughness (O. Vatel et al,: Jpn, J, Appl. Phys. Vol. 32, pp. L1489, 1993). There has been no report, however, on planarization of a surface with a {100} plane at an atomic level to which the present inventors pay attention.
There have been many reports on planarization of a surface with a {100} plane by heat treatment under an ultra-high vacuum. It is difficult to introduce such a technique into a manufacturing process for a large diameter silicon substrate with a diameter of 200 mm or larger because of scale-up of a heat treatment furnace and decrease in productivity.
In aspects of manufacture and supply of silicon semiconductor substrates, an improvement on the surface roughness by the radical oxidation increases the number of the steps to thereby reduce productivity. In the current silicon substrate manufacturing process, it is general to adopt a process to apply the RCA cleaning after mirror polishing. Hereinafter, a silicon semiconductor substrate that is polished and cleaned is referred to as a mirror polished silicon semiconductor substrate. A silicon semiconductor substrate as a general term collectively includes an epitaxial silicon semiconductor substrate and the like. The surface roughness of a mirror polished silicon semiconductor substrate has a root mean square roughness (Rms) of the order of 0.12 nm. A device maker fabricating semiconductor integrated circuit devices applies the RCA cleaning to a silicon semiconductor substrate after accepting it. As described above, the RCA cleaning treatment generally leads to degradation of the surface roughness.
The Rms of a silicon semiconductor substrate after RCA cleaning in device makers is generally on the order of 0.18 nm. In a case where, in order to form a gate oxide film on the substrate, an oxide film with a thickness of the order of 5 nm is formed in a conventional dry oxygen atmosphere, the Rms of the interface is degraded to 0.22 nm. On the other hand, in a case where an oxide film with a thickness of the order of 5 nm is formed by radical oxidation after the radical sacrifice oxidation, the Rms is of the order of 0.08 nm, thereby the surface roughness being greatly reduced. While it could also be one method for decreasing the surface roughness to introduce the radical sacrifice oxidation step into a silicon semiconductor substrate maker, it leads to increase in number of steps with reduction in productivity. Accordingly, in a case of manufacturing a silicon semiconductor substrate used in fabrication of a semiconductor integrated device, it is necessary to manufacture a silicon semiconductor substrate low in surface roughness without applying sacrifice oxidation such as radical oxidation or special cleaning.